Coala的“vhdllintbear”熊（http://coala.rtfd.org/）
VHDLLintBear的Python项目详细描述
检查vhdl代码是否存在常见的代码样式问题。
Rules include:
- Signals, variables, ports, types, subtypes, etc. must be lowercase.
- Constants and generics must be uppercase.
- Entities, architectures and packages must be “mixedcase” (may be 100% uppercase, but not 100% lowercase).
- Ports must be suffixed using _i, _o or _io denoting its kind.
- Labels must be placed in a separated line. Exception: component instantiation.
- End statements must be documented indicating what are finishing.
- Buffer ports are forbidden.
- VHDL constructions of the “entity xxxx is” and similars must be in one line. You can’t put “entity xxxxx” in one line and “is” in another.
- No more than one VHDL construction is allowed in one line of code.
有关详细信息，请参见<；http://fpgalibre.sourceforge.net/ingles.html#tp46>；。 信息。
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