用于解析Devicetree源v1的库
pydevicetree的Python项目详细描述
pydevicetree公司
这是一个python3库，用于解析、查询和修改Devicetree源v1文件 在Devicetree Specification v0.2中描述。在
安装
pydevicetree支持Python>；=3.5，可以使用Python Package Index中的pip安装。在
pip install pydevicetree
教程
设备树
假设你有档案设计.dts带着里面的东西
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "my,design";
aliases {
serial0 = "/soc/uart@10000000";
};
chosen {
stdout-path = "/soc/uart@10000000:115200";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imac";
status = "okay";
timebase-frequency = <1000000>;
sifive,dtim = <&dtim>;
interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "my,design-soc";
ranges;
dtim: dtim@20000000 {
compatible = "sifive,dtim0";
reg = <0x20000000 0x10000000>;
reg-names = "mem";
};
uart: uart@10000000 {
compatible = "sifive,uart0";
reg = <0x10000000 0x1000>;
reg-names = "control";
};
};
};
解析树
解析树很容易，1，2。。。在
^{pr2}$查询树
按compatible字符串
>>> tree.match("sifive,rocket0")
[<Node cpu>]
按路径
>>> tree.get_by_path("/soc/dtim")
<Node dtim@20000000>
路径中允许设备树别名
>>> tree.get_by_path("serial0")
<Node uart@10000000>
获取Node属性
属性的值（或列表/数组的第一个值）可以用Node.get_field()来检索
>>> tree.match("sifive,rocket0")[0].get_field("timebase-frequency")
1000000
可以使用Node.get_fields()检索分配给属性的值列表或数组
>>> tree.match("sifive,rocket0")[0].get_fields("compatible")
<StringList ['sifive,rocket0', 'riscv']>
对于reg和ranges，有帮助器方法Node.get_reg()和{
>>> tree.get_by_path("/soc/dtim").get_reg()
<RegArray [536870912, 268435456]>
>>> tree.get_by_path("/soc/dtim").get_reg().get_by_name("mem")
(536870912, 268435456)
>>> "0x%x" % tree.get_by_path("/soc/dtim").get_reg().get_by_name("mem")[0]
'0x20000000'
获取chosen属性
Devicetree.chosen()提供对chosen节点属性的快速访问
>>> tree.chosen("stdout-path")
<StringList ['/soc/uart@10000000:115200']>
转换回Devicetree
任何树或子树都可以通过调用Node.to_dts()或简单地转换回Devicetree
通过print操作：
>>> print(tree.match("sifive,rocket0")[0])
cpu@0 {
#size-cells = <0>;
compatible = "sifive,rocket0", "riscv";
device_type = "cpu";
reg = <0x0>;
riscv,isa = "rv32imac";
status = "okay";
timebase-frequency = <1000000>;
sifive,dtim = <&dtim>;
interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
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